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SPT7870
10-BIT, 100 MSPS ECL A/D CONVERTER
FEATURES
* * * * * * * * * 10-Bit, 100 MSPS Analog-to-Digital Converter Monolithic Bipolar Single-Ended Bipolar Analog Input -1.0 V to +1.0 V Analog Input Range Internal Sample-and-Hold Internal Voltage Reference Programmable Data Output Formats Single Ended ECL/PECL Outputs TTL Version Available as the SPT7871
APPLICATIONS
* * * * * Professional Video HDTV Communications Imaging Digital Oscilloscopes
GENERAL DESCRIPTION
The SPT7870 is a 10-bit, 100 MSPS analog-to-digital converter, with a two stage sub-ranging flash/folder architecture. The bipolar, single-ended analog input provides an easy interface for most applications. Programmable data output formats provide additional ease of implementation and flexibility. The device supports high-speed ECL- and PECL-level outputs.
The resolution and performance of this device makes it well suited for professional video and HDTV applications. The onchip track-and-hold provides for excellent AC performance enabling this device to be a converter of choice for RF communications and digital sampling oscilloscopes. The SPT7870 is available in a 44L cerquad package in the industrial temperature range and in die form.
VEE
VCC
BLOCK DIAGRAM
Analog Input
VIN T/H D10 (Overrange)
T/H
8-Bit Folder ADC (LSB)
D9 (MSB) D8 D7 D6
3-Bit Flash (MSB)
3-Bit DAC
Error Correction Logic
Output Latch And Buffers
D5 D4 D3 D2
Internal +1.0 V Reference VT* Reference Ladder Timing and Control VB* Internal -1.0 V Reference
D1 D0
VM*
MINV LINV CLK NCLK
* Provided for reference decoupling purposes only.
AGND
DGND
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA Phone: (719) 528-2300 FAX: (719) 528-2370 E-Mail: www.spt.com
ABSOLUTE MAXIMUM RATING (Beyond which damage may occur)1
Supply Voltages VCC ........................................................................... 0 to +6.5 V VEE ............................................................................. 0 to -6.5 V Input Voltages Analog Input ............................................. VEEVINVCC LINV/MINV Inputs ......................... -0.5 V to VCC + 0.5 V CLK/NCLK Inputs ........................................... VEE to 0 V Output Digital Outputs ......................................... +30 to -30 mA Temperature Operating Temperature ............................. -40 to + 85 C Junction Temperature ........................................ + 175 C Lead, Soldering (10 seconds) ............................ + 300 C Storage .................................................... -60 to + 150 C
Note: 1. Operation at any Absolute Maximum Ratings is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
TA=+25 C, VCC=+5.0 V, VEE=-5.2 V, VIN=1.0 V, fClock=80 MHz, 50% clock duty cycle, unless otherwise specified.
PARAMETERS DC Performance Resolution Differential Linearity Integral Linearity, Best Fit No Missing Codes Analog Input Input Voltage Range Input Bias Current Input Resistance Input Capacitance Input Bandwidth FS Offset Error Timing Characteristics Maximum Conversion Rate Minimum Conversion Rate Pipeline Delay (Latency) Transient Response Overvoltage Recovery Time Output Delay (td) Aperture Delay Time Aperture Jitter Time Dynamic Performance Effective Number of Bits fIN =10 MHz fIN = 25 MHz fIN = 25 MHz fIN = 50 MHz fIN = 50 MHz Signal-To-Noise Ratio fIN =10 MHz fIN = 25 MHz fIN = 25 MHz fIN = 50 MHz fIN = 50 MHz Total Harmonic Distortion1 fIN = 10 MHz fIN = 25 MHz fIN = 25 MHz fIN = 50 MHz fIN = 50 MHz
TEST CONDITIONS
TEST LEVEL
MIN
TYP 10 0.5 1.0 2.5 Guaranteed 1.0 25 150 100 5 180 20
MAX
UNITS Bits LSB LSB LSB
fClock = 6.4 MHz fClock = 6.4 MHz Full Temperature fClock = 6.4 MHz
I I V I V I I V V IV I IV V IV V V V V V
-1.0
+1.25 2.0
-100 50
100
Full Temperature Full Power
150
100
V A k k pF MHz mV MSPS MSPS Clock ns ns ns ns ps (rms)
100 2 2 10 10 3 1 5
fClock = 100 MHz fClock = 100 MHz
I I V I V I I V I V I I V I V
8.1 8.1 7.4
8.5 8.5 8.0 7.8 7.5 55 54 51 54 50 -63 -60 -56 -51 -50
Bits Bits Bits Bits Bits dB dB dB dB dB dBc dBc dBc dBc dBc
52 52 52
fClock = 100 MHz fClock = 100 MHz
-56 -55 -47
fClock = 100 MHz fClock = 100 MHz
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ELECTRICAL SPECIFICATIONS
TA=+25 C, VCC=+5.0 V, VEE=-5.2 V, VIN=1.0 V, fClock=80 MHz, 50% clock duty cycle, unless otherwise specified.
PARAMETERS Dynamic Performance Signal-to-Noise & Distortion (SINAD) fIN = 10 MHz fIN = 25 MHz fIN = 25 MHz fIN = 50 MHz fIN = 50 MHz Spurious Free Dynamic Range fIN = 10 MHz fIN = 25 MHz fIN = 50 MHz Two-Tone Intermodulation Dist. Rejection2 Differential Phase Differential Gain Power Supply Requirements +VCC Supply Voltage - VEE Supply Voltage +VCC Supply Current - VEE Supply Current Power Dissipation Power Supply Rejection Ratio Digital Inputs LINV, MINV Clock Inputs Logic 1 Voltage Logic 0 Voltage Maximum Input Current Low Maximum Input Current HIgh Pulse Width Low (tpwl) Pulse Width High (tpwh) Rise/Fall Time Digital Outputs Logic 1 Voltage (ECL) Logic 0 Voltage (ECL) Logic 1 Voltage (PECL) Logic 0 Voltage (PECL) trise tfall
TEST CONDITIONS
TEST LEVEL
MIN
TYP
MAX
UNITS
fClock = 100 MHz fClock = 100 MHz
I I V I V V V V V V V IV IV VI VI VI IV V VI VI VI VI IV IV IV VI VI IV IV V V
51 51 46.5
54 53 50 48 47 65 62 52 -65 0.5 1
dB dB dB dB dB dB FS dB FS dB FS dBc Degree % 5.25 -5.45 151 240 2.0 V V mA mA W dB Logic V V A A ns ns ns V V V V ns ns
4.75 -4.95
5.0 -5.2 127 202 1.7 30 CMOS/TTL
-1.1 -100 -100 4.0 4.0 -1.5 +100 +100 250 250 1.5 -0.9 -1.7 4.1 3.3 2.0 2.0
20% to 80% 50 to -2 V, DGND=0.0 V 50 to -2 V, DGND=0.0 V 50 to +3 V, DGND=+5.0 V 50 to +3 V, DGND=+5.0 V 10% to 90% 10% to 90%
-1.1 3.9
-1.5 3.5
12048 pt FFT using distortion harmonics 2 through 10. 2Measured as a second order (f1-f2) intermodulation product from a two-tone test, with each input tone at 0 dBm.
TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition.
TEST LEVEL I II III IV V VI
TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA=25 C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = 25 C. Parameter is guaranteed over specified temperature range. SPT7870
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Figure 1 - Timing Diagram
N tclk tpwh tpwl N+1 N+2
Table I - Data Output Timing Parameters Timing Parameter Min Typ Max fclock 2 MHz 100 MHz Clock Pulse Width High (tpwh) 4.0 ns 250 ns Clock Pulse Width Low (tpwl) 4.0 ns 250 ns Switching Delay (td) 3 ns Clock Latency 2 clock cycles
DATA VALID N
CLK
td
OUTPUT DATA N-3 N-2 DATA VALID N-1
THEORY OF OPERATION
The SPT7870 uses a two stage subranging architecture incorporating a 3-bit flash MSB conversion stage followed by an 8-bit interpolating folder conversion stage. Digital error correction logic combines the results of both stages to produce a 10-bit data conversion digital output. The analog signal is input directly to the 3-bit flash converter which performs a 3-bit conversion and in turn drives an internal DAC used to set the second stage voltage reference level. The 3-bit result from the flash conversion is input to the digital error correction logic and used in calculation of the upper most significant bits of the data output. The analog input is also input directly to an internal track-andhold amplifier. The signal is held and amplified for use in the second stage conversion. The output of this track-and-hold is input into a summing junction that takes the difference between the track-and-hold amplifier and the 3-bit DAC output. The residual is captured by a second track-and-hold which holds and amplifies this residual voltage. The residual held by the track-and-hold amplifier is input to an 8-bit interpolating folder stage for data conversion. The 8-bit converted data from the folder stage is input into the digital error correction logic and used in calculation of the lower significant bits. The error correction logic incorporates a proprietary scheme for compensation of any internal offset and gain errors that might exist to determine the 10-bit conversion result. The resultant 10 bit data conversion is internally latched and presented on the data output pins via buffered output drivers.
should both be connected to the analog ground plane. All other -5.2 V requirements of the external digital logic circuit should be connected to the digital ground plane. Each power supply pin should be bypassed as closely as possible to the device with .01 F and 2.2 F capacitors as shown in figure 2. The two grounds available on the SPT7870 are AGND and DGND. DGND is used only for ECL outputs and is to be referenced to the output pulldown voltage. These grounds are not tied together internal to the device. The use of ground planes is recommended to achieve the best performance of the SPT7870. The AGND and the DGND ground planes should be separated from each other and only connected together at the device through an inductance or ferrite bead. Doing this will minimize the ground noise pickup. ANALOG INPUT The SPT7870 has a single-ended analog input with a bipolar input range from -1 V to +1 V. The bipolar input allows for easier interface by external op amps when compared to unipolar input devices. Because the input common mode is 0 V, the external op amp can operate without a voltage offset on the output, thereby maximizing op amp head room and minimizing distortion. In addition, the 0 V common mode allows for a very simple DC coupled analog input connection if desired. The current drive requirements for the analog input are minimal when compared to conventional flash converters due to the SPT7870's low input capacitance of only 5 pF and very high input impedance of 150 k. CLOCK INPUTS The clock inputs are designed to be driven differentially with ECL levels. For optimal noise performance, the clock input rise time should be a maximum of 1.5 ns. Because of this, the use of fast logic is recommended. The analog input signal is latched on the rising edge of the CLK. The clock may be driven single-ended since the NCLK pin is internally biased to -1.3 V. NCLK may be left open but a .01 F bypass capacitor from NCLK to AGND is recommended. NOTE: System performance may be degraded due to increased clock noise or jitter. The performance of the SPT7870 is specified and tested with a 50% clock duty cycle. However, at sample rates greater
TYPICAL INTERFACE CIRCUIT
The SPT7870 requires few external components to achieve the stated operation and performance. Figure 2 shows the typical interface requirements when using the SPT7870 in normal circuit operation. The following section provides a description of the pin functions and outlines critical performance criteria to consider for achieving the optimal device performance. POWER SUPPLIES AND GROUNDING The SPT7870 requires the use of two supply voltages, VEE and VCC. Both supplies should be treated as analog supply sources. This means the VEE and VCC ground returns of the device
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than 80 MSPS, additional gains in dynamic performance of the device may be obtained by adjusting the clock duty cycle. Typically, operation between 55 to 60% duty cycle will yield improved results. INTERNAL VOLTAGE REFERENCE The SPT7870 incorporates an on-chip voltage reference. The top and bottom reference voltages are each internally tied to their respective top and bottom of the internal reference ladder. The pins for the voltage references and the ladder (including the center of the ladder) are brought out to pins on the device for decoupling purposes only (pins VT, VM, and VB). A .01 F capacitor should be used on each pin and tied to AGND. See the typical interface circuit (figure 2). The internal voltage reference and the internal error correction logic eliminate the need for driving externally the voltage reference ladder. In fact, the voltage reference ladder should not be driven with an external voltage reference source as the internal error correction circuitry already compensates for the internal voltage and no improvement will result.
DIGITAL OUTPUT DATA TIMING The data is presented on the output pins two clock cycles after the input is sampled with an additional output delay of typically 3 ns. The data is held valid for one clock cycle. Refer to the timing diagram shown in figure 1. DIGITAL OUTPUT CONTROL PINS - MINV, LINV Two digital output control pins control the digital output format. See table III. The MINV pin is a CMOS/TTL-compatible input. It inverts the most-significant bit (D9) when tied to +5 V. The MSB (D9) is noninverted when MINV is tied to ground or floated. The MINV pin is internally pulled down to ground. The LINV pin is a CMOS/TTL-compatible input. It inverts the least-significant bits (D8 through D0) when tied to +5 V. The least-significant bits (D8 through D0) are noninverted when LINV is tied to ground or floated. The LINV pin is internally pulled down to ground. Table III - Data Output Bits MINV 0V 0V +5 V +5 V LINV 0V +5 V 0V +5 V Description of Data Binary (Noninverted) Two's Complement (Inverted) Two's Complement (Noninverted) Binary (Inverted)
DIGITAL OUTPUTS
DIGITAL OUTPUT DATA FORMAT - D0 - D9 D0 is the least-significant bit for the digital data output, and D9 is the most-significant bit. Four data output formats are available and are controlled by the MINV and LINV pins. Table III shows the four possible output formats possible as a function of MINV and LINV. Table II shows the output coding data format versus analog input voltage relationship. Table II - Output Coding Data Format
VIN >+1.0 V (+FS) +1.0 V -1 LSB 0.0 V -1.0 V +1 LSB (-FS) <-1.0 V D10 D9...D0 (Binary*) D9...D0 (2's Comp*) 1 0 0 0 0 0 0 0 11 1111 1111 11 1111 1111 11 1111 1110 10 0000 0000 01 1111 1111 00 0000 0001 00 0000 0000 00 0000 0000 01 1111 1111 01 1111 1111 01 1111 1110 00 0000 0000 11 1111 1111 10 0000 0001 10 0000 0000 10 0000 0000
ECL AND PECL DIGITAL OUTPUT LEVELS The SPT7870 supports ECL (10K and 100K compatible) and PECL logic levels. It has single-ended output drive capability. ECL termination resistors of 50 to -2 V are required as shown in the typical interface circuit in figure 2. To interface to PECL logic levels, supply +5 V to DGND and terminate the digital outputs through 50 resistors to +3 V.
THERMAL MANAGEMENT
SPT recommends that a heat sink be used for this device to ensure rated performance. A heat sink in still air provides adequate thermal performance under laboratory tests. Air flow may be required for operation at elevated ambient temperature. SPT recommends that the junction temperature be maintained under +150 C. The thermal impedance values for the cerquad package are JC = 3.3 C/W and JA = 70 C/W (junction to ambient in still air with no heat sink).
*Refer to table III for possible output formats. OVERRANGE BIT - D10 D10 is the overrange bit which is asserted whenever the analog input signal exceeds the positive full scale input by 1 LSB. When this condition occurs the D10 bit will be asserted to logic high and remain high continuously until the overrange condition is removed from the input. All other output signals will also stay at their maximum encoded output throughout this condition. D10 is not asserted for an underscale condition when the input exceeds the negative full scale.
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TYPICAL PERFORMANCE CHARACTERISTICS
Power Relative to ADC Full Scale (dB)
70 65 60 THD SNR Dynamic Performance vs. Input Frequency Sample Rate = 80 MSPS
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 0
Single Tone at 14.9 MHz Sample Rate = 80 MSPS
dB
55 50 SINAD 45 40
0
20
40 60 80 Input Frequency (MHz)
100
10
20 Frequency (MHz)
30
40
Dynamic Performance vs. Input Frequency Sample Rate=100 MSPS, 50% Clock Duty Cycle 60 55 50
Dynamic Performance vs. Input Frequency Sample Rate=100 MSPS, 60% Clock Duty Cycle 60 THD 55 SNR
THD SNR
50
dB
dB
SINAD 45 40 35
45 SINAD 40 35
0
20
40 60 80 Input Frequency (MHz)
100
0
20
40 60 80 Input Frequency (MHz)
100
65 60
Dynamic Performance vs. Sample Rate Input Frequency = 25MHz THD
65
Dynamic Performance vs. Temperature Sample Rate = 80 MSPS Input Frequency = 25 MHz
THD 60
55
dB
SNR 50
dB
55
SINAD 45 40
SNR
SINAD
60 70 80 90 100 Sample Rate (MSPS) 110
50 -25
0
25 50 Temperature (C)
75
100
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Figure 2 - Typical Interface Circuit
+A5 -A5.2
Figure 3 - SPT7870 Clock Input Equivalent Circuit
AVCC
*
*
(ESD) 26 k
AGND (ESD)
VCC AGND VEE DGND
6 k NCLK
Analog Input
.01
D10 VIN VT .01 VM .01 VB D5 D4 D3 D9 D8
CLK 26 k 52 k (ESD) -1.3 V
(ESD)
D7 D6
Interfacing Logic
VEE
SPT7870
ECL Differential Clock Input
CLK
D2 D1
Figure 4 - SPT7870 Digital Outputs Equivalent Circuit
AGND DGND
CLK MINV LINV D0
+A5 +A5 10 F + -A5.2 10 F + FB1 -D2
50 -D2 V -D5.2 10 F + 10 F + -D5.2
(ESD)
ECL/PECL OUT
+5 V AGND -5.2 V -2 V DGND -5.2 V
Notes: 1) = Line termination. 2)
(ESD)
* = 0.01 F chip capacitor in parallel with 2.2 F Tantalum capacitor.
VEE
3) Immediate output buffer is highly recommended to optimize the performance due to reflection.
PACKAGE OUTLINE
44L Cerquad
SYMBOL A B
44
INCHES MIN 0.550 typ 0.685 0.037 0.016 typ 0.008 typ 0.027 0.006 typ 0.080 0.150 0.051 0.709 0.041 MAX
MILLIMETERS MIN 13.97 typ 17.40 0.94 0.41 typ 0.20 typ 0.69 0.15 typ 2.03 3.81 1.30 18.00 1.04 MAX
C D E F
C
1
D
A
B
G H
0 - 5
H E F G
A B
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PIN ASSIGNMENTS
DGND DGND AGND AGND LINV N/C VCC VEE VEE VCC N/C
PIN FUNCTIONS
NAME VIN D0-D9
33 32 31 30 29
I/O I O O I I I
DESCRIPTION Analog Input Digital Output Data (D0 = LSB) Overflow Clock (Internal Pull-Down to Ground) Inverted Clock (Internal Pull-Down to -1.3 V) Invert Least Significant Bits (D0-D8); CMOS/TTL Level; Invert=+5 V; Internal Pull-Down to Ground Invert MSB (D9); CMOS/TTL Level; Invert=+5 V; Internal Pull-Down to Ground Internal Top Reference Decoupling (+1 V typical) Internal Mid-Point Reference Decoupling (0 V typical) Internal Bottom Reference Decoupling (-1 V typical) +5 V Analog Supply -5.2 V Supply Not Connected Analog Ground Digital Ground
43
40
37
44
41
38
42
39
36
35
34
DO D1 D2 D3 D4 D5 D6 D7 D8 D9 D1O
1 2 3 4 5 6 7 8 9 10 11
VB N/C N/C VM N/C VIN N/C N/C VT VCC VCC
D10 CLK NCLK LINV
44L Cerquad
28 27 26 25 24 23
MINV
13 16 19 12 15 18 14 17
I
DGND
CLK
20
21
DGND
AGND
AGND
MINV N/C
NCLK N/C
VEE
VEE
22
VT VM VB VCC VEE N/C AGND DGND
N/A N/A N/A I I I I
ORDERING INFORMATION
PART NUMBER SPT7870SIQ SPT7870SCU TEMPERATURE RANGE -40 to +85 C +25 C PACKAGE 44L Cerquad Die*
*Please see the die specification for guaranteed electrical performance.
Signal Processing Technologies, Inc. reserves the right to change products and specifications without notice. Permission is hereby expressly granted to copy this literature for informational purposes only. Copying this material for any other use is strictly prohibited. WARNING - LIFE SUPPORT APPLICATIONS POLICY - SPT products should not be used within Life Support Systems without the specific written consent of SPT. A Life Support System is a product or system intended to support or sustain life which, if it fails, can be reasonably expected to result in significant personal injury or death. Signal Processing Technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device failure. It is therefore not recommended, and exposure of a device to such a process will void the product warranty.
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